Differential amplifier

ABSTRACT

In a semiconductor differential amplifier comprising a differential pair of npn transistors having the emitters connected to the emitter of lateral transistors, the bases supplied with an input signal, and the collectors connected in common to one terminal of the voltage source so as to derive the output signal from the collector of the lateral transistor, the emitter voltage of each of the differential pair transistors is applied to the common base of the pnp lateral transistors through a constant voltage element consisting of a transistor or a diode. Therefore, the voltage applied between the base and the substrate of the lateral transistor is reduced and hence the tolerance to the reverse breakdown voltage is increased and simplification of the circuit structure becomes possible. Further, a sink current path is provided between the base of the pnp lateral transistor and the other terminal of the voltage source to allow a stabilized bias current to flow through the differential amplifier.

BACKGROUND OF THE INVENTION

1. FIELD OF THE INVENTION

This invention relates to a differential amplifier and more particularly to a differential amplifier comprising an input stage including npn transistors and pnp lateral transistors.

2. DESCRIPTION OF THE PRIOR ART

Conventionally, the circuit of FIG. 5 has been used in the μA 741 type operational amplifier, commercially available from Fairchild Inc., U.S.A., and has been known as an input circuit for operational amplifiers produced in a monolithic semiconductor integrated circuit form. See, for example, U.S. Pat. No. 3,586,987 issued on June 22, 1971. The input stage of this circuit is formed of integrated npn transistors Q₁ and Q₂ having a high current amplification factor and integrated pnp lateral transistors Q₃ and Q₄ having a low current amplification factor for minimizing the bias current. Since the reverse breakdown voltage of the base-emitter junction BV_(EBO) of the integrated lateral pnp transistor is high, whereas that of the npn transistor is relatively poor, the range of the differential input voltage can be set wide. As the pnp lateral transistors Q₃ and Q₄ are biased with a constant sink current I_(B) and if the base-emitter voltage V_(BE) matching between the differential pair transistors Q₁ and Q₂ and the transistors Q₇ and Q₈ serving as the active loads thereof are arranged well, the collector currents through the respective elements become substantially equal. The active loads of high resistance are provided with the transistors Q₇ and Q₈ for obtaining high gain. The introduction of these active loads into the design of monolithic operational amplifiers is disclosed by R. J. Widlar in "Design techniques for monolithic operational amplifiers" IEEE J. Solid-State Circuits SC-4, No. 4, p. 184, Aug. 1969.

Generally, the dispersion or unevenness in the characteristics of lateral transistors is large. Hence, a diode Q₅ ', formed by a pnp transistor having its collector connected to its base, and a transistor Q₆ ' are used to effect current feed-back for stabilizing the operation of the lateral transistors Q₃ and Q₄. The diode Q₅ ' which may practically be a diode-connection transistor, detects the current flowing through the transistors Q₁ and Q₂ and settles the collector current of the transistor Q₆ ' in correspondence thereto. Since a sink current I_(B) is controlled by the base input of an npn transistor Q₉ and is held constant, and the differential current of the collector current of the transistor Q₆ ' and the sink current I_(B) controls the base current of the transistors Q₃ and Q₄, the bias stability and the common mode signal rejection ratio (CMRR) increase. Further, the prevention of oscillation can be made easily by connecting a phase-compensating capacitor between the bases of the transistors Q₇ and Q₈ and -V_(EE) terminal of the transistor Q₇ (Q₈) as the active load.

In this circuit, however, since the source voltage V_(CC) is directly applied to the lateral transistors Q₅ ' and Q₆ ' for the purpose of current feed-back (in the case where the diode Q₅ ' is a diode connection transistor), a high voltage is applied between the base and the substrate of these transistors and there arises a problem in the reverse breakdown voltage. Further, there are limitations in the modification of the circuit structure and a simplification of the circuit is hardly ever made.

SUMMARY OF THE INVENTION

This invention is made to solve the above problems and therefore an object of this invention is to provide a differential amplifier suited for semiconductor integrated circuits in which the voltage applied to the lateral transistors is reduced while keeping the high common mode signal rejection ratio, stability and high frequency characteristics.

Another object of this invention is to provide a differential amplifier suited for semiconductor integrated circuits capable of various circuit modifications and simplifications.

According to one aspect of this invention, there is provided a differential amplifier comprising differential pair npn transistors each having a base supplied with an input signal and an emitter, at least one lateral pnp transistor having an emitter connected to the emitter of one of said npn transistors and a collector supplying an output, the emitter voltage of the other of said npn transistors being applied to the base of said pnp transistor through a constant voltage element, and a current path being provided between the base of said pnp transistor and the negative terminal of a voltage source.

The above and other objects, features and advantages of this invention will become apparent from the following detailed description of the preferred embodiments of the invention when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a differential amplifier according to an embodiment of this invention.

FIG. 2 is a circuit diagram of a differential amplifier according to another embodiment of this invention.

FIG. 3 is a circuit diagram of a modification of the circuit of FIG. 2.

FIG. 4 is a circuit diagram of a pre-amplifier embodying an embodiment of this invention.

FIG. 5 is a circuit diagram of an example of the conventional differential amplifier.

Throughout the drawings, similar references denote similar parts.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinbelow, description will be made of the preferred embodiments in detail referring to the accompanying drawings.

FIG. 1 is a circuit diagram of a differential amplifier produced in the form of silicon semiconductor integrated circuits according to an embodiment of this invention.

The input stage of the differential amplifier utilizes complementary elements and comprises differential pair npn transistors Q₁ and Q₂ of high current amplification factor, each having an emitter, pnp lateral transistors Q₃ and Q₄ of low current amplification factor, each having an emitter, and resistors R₄ and R₇ connected between the emitters of the npn transistors and the pnp transistors, respectively. Other npn transistors Q₇ and Q₈ are connected to the collector of the lateral pnp transistors Q₃ and Q₄ as the active loads. The collector and the base of the transistor Q₇ are connected together and the base thereof is connected to the base of the transistor Q₈ for driving transistors Q₇ and Q₈ with a constant current. The emitters of the transistors Q₇ and Q₈ are connected to a negative terminal -V_(EE) through emitter resistors R₁ and R₂. The bias voltage for the pnp lateral transistors Q₃ and Q₄ is controlled by pnp lateral transistors Q₅ and Q₆. The emitters of the transistors Q₅ and Q₆ are connected to the emitters of the npn transistors Q₁ and Q₂ through emitter resistors R₅ and R₆, the bases of transistors Q₅ and Q₆ to the bases of the pnp transistors Q₃ and Q₄ in common, and the collectors of transistors Q₅ and Q₆ to their common bases and to the collector of a transistor Q₉. The transistor Q₉ forms a constant sinking current circuit providing a constant sinking current and sets the bias current of the differential amplifier circuit. The bias control at the base of the transistor Q₉ may be effectively utilized. The input signal for this differential amplifier is applied between the bases of the differential pair npn transistors Q₁ and Q₂ and the output thereof is derived from the collector of one of the pnp lateral transistors, Q₄ (or Q₃). A capacitor C₁ may preferably be connected as shown by broken lines for preventing oscillation.

In the differential amplifier circuit of the above structure, the emitter voltage of the npn transistor Q₁ (or Q₂) is supplied to the base of the pnp lateral transistor Q₃ (or Q₄), which forms an input stage with the differential pair npn transistor Q₁ (or Q₂), through the emitter-base of the lateral transistor Q₅ (or Q₆) which serves as a constant voltage element. Therefore, the base of the pnp lateral transistor Q₃ (or Q₄) is given a constant bias voltage clamped by the base-emitter constant voltage of the transistor Q₅ (or Q₆) and the transistor Q₁ (or Q₂) from a base voltage of the transistor Q₁ (or Q₂). Further, since the transistors Q₅ and Q₆ are driven with a constant sink current supplied through the transistor Q₉, a stabilized bias current is allowed to flow through the differential amplifier. Since the emitter-base paths of the transistors Q₅ and Q₆ are respectively connected in parallel with the emitter-base paths of the transistors Q₃ and Q₄, the stability of the biasing for the lateral transistors Q₃ and Q₄ of the input stage is excellent for changes in the ambient temperature or variations in the electrical characteristics of the pnp transistors. Since the input stage is formed of a complementary bipolar transistor structure including npn transistors and pnp transistors, the range of the differential input voltage is wide. Additionally, phase compensation can be achieved easily by adding a capacitor C₁, and the common mode signal rejection ratio can be set large. Further, since the pnp lateral transistors Q₅ and Q₆ are not connected directly to the voltage source terminal V_(CC), the base-substrate voltage can be reduced to about one half of the conventional value. Although a transistor as a load for the pnp transistors Q₃ and Q₄ is used in the above embodiment, a passive device, such as a resistor, may be used in place of such an active load.

Further, it will be apparent from the following description that various circuit modifications can be made and that simplification of the structure is possible.

FIG. 2 is a circuit diagram of a differential amplifier according to another embodiment of this invention. In the circuit, the emitter of a pnp lateral transistor Q₄ is connected to the emitter of one of the differential pair npn transistors Q₁ and Q₂, say Q₂, and the base thereof is connected to the emitter of the other npn transistor Q₁ through a constant voltage element, i.e., a diode Q₅ (which may be a lateral transistor having the base and the collector connected in common). The collector of the transistor Q₄ is connected to a constant current load circuit I₀₂ and the base thereof to a constant current circuit I₀₁ for setting the bias current. Namely, this circuit can be considered as a simplified version of the circuit of FIG. 1 with the transistors Q₃ and Q₆ dispensed with.

FIG. 3 shows another embodiment in which a diode Q₆ is added between the base and the emitter of the transistor Q₄ for improving the balance of the differential amplifier of FIG. 2. In this circuit, when the dc current through the collectors of the transistors Q₁ and Q₂ are respectively two parts, the constant sink current I₀₁ ' may be three parts and I₀₂ ' one part.

Further, in the circuit of FIG. 1, the emitter resistors R₄ to R₇ may be dispensed with if the operation points of the active elements used are suitably selected.

FIG. 4 shows a circuit of an audio preamplifier embodying an embodiment of the differential amplifier circuit of this invention. The circuit is formed in one silicon chip by integrated circuit technology. The first stage amplifier is formed of a differential amplifier of this invention and the output stage is formed of a push-pull circuit including an npn transistor Q₁₅ and a pnp transistor Q₁₆. Transistors Q₁₀ and Q₁₁ and a resistor R₄ constitute a common bias line; the transistor Q₁₁ biasing the first stage amplifier and the transistor Q₁₀ biasing the output stage amplifier. The dc output voltage is negatively fed back to the base of the transistor Q₂ so as to reduce the offset voltage. Transistors Q₁₃ and Q₁₄ are driver transistors for the push-pull circuit.

This invention can be utilized widely as a differential amplifier circuit in, of course, high power operational amplifiers and also other applications. 

What is claimed is:
 1. A differential amplifier comprising:an input amplifier stage comprising a first pair of npn transistors having collector electrodes connected to a first voltage supply, base electrodes forming input terminals of said differential amplifier and emitter electrodes, and a second pair of pnp transistors each having an emitter electrode connected to the emitter electrode of a corresponding one of said first pair of npn transistors, a base electrode and a collector electrode; a third pair of pnp transistors each having a base electrode connected to its collector electrode and having substantially the same operating characteristics as those of said second pair of pnp transistors, each transistor of said third pair of pnp transistors having an emitter electrode connected to the emitter of a corresponding one of said second pair of pnp transistors, each transistor of said third pair of pnp transistors having a base electrode connected to the base electrode of the corresponding one of said second pair of pnp transistors, thereby providing bias currents through said second pair of pnp transistors and compensating for changes in operating characteristics of said second pair of pnp transistors due to temperature fluctuations; bias circuit means connected to the base electrodes of said third pair of pnp transistors for supplying bias currents therein;load circuit means connected to the collector electrodes of said second pair of pnp transistors for providing at one of the collector electrodes of said second pair of pnp transistors, differential voltage changes having a correspondence to the variations between input signals applied to said input terminals; and output means connected to the collector electrode of one of said second pair of pnp transistors for deriving said differential voltage changes as an output signal of said differential amplifier.
 2. The differential amplifier according to claim 1, in which said load circuit means comprises a fourth pair of npn transistors having commonly connected base electrodes, with each collector electrode being connected to the corresponding one of the collector electrodes of said second pair of pnp transistors, and emitter electrodes of said fourth pair of npn transistors connected to a second coltage supply of opposite polarity from said first voltage supply, the collector electrode of one of said fourth pair of npn transistors being connected to its base electrode, the collector electrode of the other of said fourth pair of npn transistors being connected to said output means.
 3. The differential amplifier according to claim 2, in which a capacitor is connected between the commonly connected base electrodes of said fourth pair of npn transistors and the second voltage supply to provide a phase-compensated output signal at the output means.
 4. The differential amplifier according to claim 1, wherein all of said circuit elements are formed on a monolithic semiconductor substrate.
 5. The differential amplifier according to claim 1, in which said emitter electrodes of said first pair of npn transistors are connected through respective resistors with the emitter electrodes of said second and third pairs of pnp transistors.
 6. The differential amplifier according to claim 1, in which said bias circuit means comprises an npn transistor having a base adapted to receive a bias control signal and a collector connected to said base electrodes of said third pair of pnp transistors. 